Error rate estimating device, method, and information recording medium

ABSTRACT

To reduce the size of the device for judging the error rate on a channel and reducing the amount of processing, a normalization accumulator cumulatively adds the number of times that normalization is performed within a predetermined time in an ACS circuit calculating a state metric. The table stores a table establishing correspondence between the number of times of normalization cumulatively added by the normalization accumulator. The table uses the stored table to judge and output an error rate corresponding to the input cumulative number of times of normalization.

TECHNICAL FIELD

The present invention relates to an error rate estimating device and areceiver using the error rate estimating device, an error rateestimating method and a receiving method using the error rate estimatingmethod, and an information recording medium, more particularly relatesto an error rate estimating device and method for determining an errorrate on a channel using the number of times of normalization performedby a circuit finding a state metric, a receiver using the error rateestimating device, an error rate estimating method and a receivingmethod using the error rate estimating method, and an informationrecording medium.

BACKGROUND ART

At the present, in Japan, provision of a digital broadcasting serviceusing a successor to the BS4 scheduled to be launched as a broadcastingsatellite is being discussed at the Radio Regulatory Council. In thisdigital broadcasting service, 8 SPK (Phase Shift Keying), QPSK(Quadrature PSK), and BPSK (Binary PSK) are defined as channel codingsystems.

FIG. 1 is a block diagram of an example of the configuration of atransmitter and a receiver. The transmitter 1 is comprised of a video,audio, or other information source 2, a coder 3, a puncturing unit 4,and a mapping unit 5. The information source 2 outputs data to be codedand transmitted to the coder 3. The coder 3 performs trellis coding oninput 1-bit data by the coding rate R=1/2 and outputs it to thepuncturing unit 4 as a 2-bit coded word. The puncturing unit 4 puncturesthe input 2-bit data and outputs it to the mapping unit 5. The mappingunit 5 assigns the input 2-bit coded word to one signal point among foursignal points shown in FIG. 5 by an quadrature modulation system andoutputs an I-signal and Q-signal of the signal point to a channel 6.

A receiver 7 is comprised of a bit insertion unit 8, a decoder 9, anddecoded information 10. The bit insertion unit 8 inserts bits into thereceived signals (I, Q) input via the channel 6 and outputs them to thedecoder 9. The decoder 9 performs trellis decoding on the input signaland outputs it as decoded information 10. The decoded information 10shows decoded data. An image and sound can be obtained by reproducingthe decoded information 10 with a not shown reproducing apparatus.

Information of the state metric output from the decoder 9 is supplied toa monitoring circuit 11. The monitoring circuit 11 determines an errorrate on the channel 6 and outputs the information as error rateinformation 12. The error rate information 12, for instance, is used asdata when adjusting the orientation of the antenna for receiving thedata in a direction giving the lowest error rate.

FIG. 2 is a block diagram showing the configuration of a coder 3. Thecoder 3 is a convolutional coder. An input 1-bit data b₀ is coded to2-bit data (c₁, c₀) and output. The output 2-bit data c₁, c₀ isgenerated by calculating the data b₀ by a processor comprising delaycircuits 21 and 22 and exclusive OR circuits 23 and 24.

That is, the data b₀ is input to the delay circuit 21, the exclusive ORcircuit 23, and the exclusive OR circuit 24. The data b₀ input to thedelay circuit 21 is delayed by one unit time and output to the delaycircuit 22 and the exclusive OR circuit 23. The data input to the delaycircuit 22 is further delayed for one unit time and output to theexclusive OR circuits 23 and 24. The exclusive OR circuit 23 calculatesthe exclusive OR of the three bits of data, that is, the data b₀currently input in the coder 3, the data input to the coder 3 one timeunit before, and further the data input to the coder 3 two time unitsbefore, to generate the output data c₁.

The exclusive OR circuit 24 calculates the exclusive OR of the data b₀currently input in the coder 3 and the data input to the coder 3 twotime unit before to generate an output data c₀.

The output data (c₁, c₀) output from the coder 3 are input to thepuncturing unit 4 in this way. The puncturing unit 4 outputs the inputdata to the mapping unit 5 as is when outputting the data of the codingrate R=1/2 to the channel 6 and punctures the input data and outputs itto the mapping unit 5 when outputting data of the coding rate R=3/4 tothe channel 6.

FIGS. 3A and 3B are views for explaining the puncturing. As shown inFIG. 3A, the puncturing unit 4 punctures the input data (c₁, c₀) inaccordance with the puncturing table shown in FIG. 3B and outputs thedata (p₁, p₀).

In the puncturing table shown in FIG. 3B, “1” shows the input dataoutput as the data p₀ or data p₁ and “0” shows the input data not output(erased). For instance, the data shown in FIG. 4B is output when thedata shown in FIG. 4A is input.

That is, as shown in FIG. 4A, when data X₁ to X₆ are input as the inputdata c₁ and the data Y₁ to Y₆ are input as the input data c₀ to thepuncturing unit 4, since these are input in the order of the data c₀,c₁, when the data are sequentially input in the order of Y₁, X₁, Y₂, X₂,. . . , Y₆, X₆ to the puncturing unit 4, as shown in FIG. 4B, the dataX₁, Y₃, X₄, and Y₆ are output as the output data p₁ and the data Y₁, X₂,Y₄, and X₅ are output as the output data p₀. Note that since the outputdata is output in the order of the data p₀, p₁, the data is output fromthe puncturing unit 4 in the order of Y₁, X₁, X₂, Y₃, Y₄, X₄, X₅, andY₆.

The input data Y₁, X₁ are output as output data p₀, p₁ as is since theycorrespond to positions of the value 1 of the puncturing table, but theinput data Y₂ is deleted since it corresponds to a position of a value 0of the puncturing table. The next output data X₂ (corresponding to aposition of a value 1 of the puncturing table) is output as the data p₀.Below, in the same way, data corresponding to a position of a value 0 ofthe puncturing table are deleted and data corresponding to a position ofa value 1 of the puncturing table are output.

The data output from the puncturing unit 4 in this way are mapped ontothe signal points in the quadrature coordinate system based on theI-axis and Q-axis as shown in FIG. 5 by the mapping unit 5. The signalpoints are arranged at equal intervals 90 degrees apart. “p₁” shown inFIGS. 3A and 3B is the MSB (most significant bit) in the signal pointassignment, while “p₀” is the LSB (least significant bit) in the signalpoint assignment. That is, a signal point assignment may be expressed as(p₁, p₀).

The data mapped by the mapping unit 5 is input to the bit insertion unit8 of the receiver 7 through the channel 6. FIGS. 6A and 6B are viewsexplaining bit insertion. Bit insertion is processing opposite to thepuncturing performed in the puncturing unit 4, that is, processing foroutputting received data as is to the decoder 9 when receiving data ofthe coding rate R=1/2 and inserting deleted data (bits) when receivingdata of the coding rate R=3/4.

As shown in FIG. 6A, the bit insertion unit 8 inserts bits in the data(p′₁, p′₀) from the transmitter 1 through the channel 6 in accordancewith the depuncturing table shown in FIG. 6B and outputs the output data(c′₁, c′₀). A value 1 of the depuncturing table shown in FIG. 6Bindicates to output the input data as is, while the value 0 indicates toinsert 0 (insert a bit).

When for example input data shown in FIG. 7A (data output from thepuncturing unit 4 and shown in FIG. 4B) is input to the bit insertionunit 8, the data shown in FIG. 7B is output. The data transmitted fromthe transmitter 1 is in the order of the data p₀, p₁, so the order ofinput into the bit insertion unit 8 of the receiver 7 also becomes thedata p′₀, p′₁. Further, the order of the data output from the bitinserted unit 8 becomes the data c′₀, c′₁.

Note that the data p′₀, p′₁ show the data p₀, p₁ output from thetransmitter having the possibility of generation of error due to theeffect of noise or distortion in the channel 6.

Therefore, the data X₂ input as the input data p′₀ is data correspondingto a position of a value 0 of the depuncturing table, so is output asthe data c′₀ in a form with 0 inserted instead of the input data X₂. Thedata X₂ is output as the data c′₁. In this way, input data positioned ata value 0 is output with 0 inserted.

Data with a bit inserted by the bit insertion unit 8 in this way isoutput to the decoder 9.

FIG. 8 is a block diagram of the inner configuration of the decoder 9.The decoder 9 is comprised of a branch metric generator 31 (hereinafterreferred to as a “BM generator 31”), an add, compare, and select (ACS)circuit 32, and a path memory 33. The signal input to the decoder 9 isfirst input to the BM generator 31 calculating the square of theEuclidean distance from a received signal point with the noise anddistortion of the channel to a signal point to originally be receivedand generating the same as a branch metric. The branch metrics generatedat the BM generator 31 are cumulatively added and compared in accordancewith a convolutional coding trellis by the ACS circuit 32 to calculatethe state metric of each state.

FIG. 9 is a trellis transition diagram for explaining the calculation ofa state metric performed by the ACS circuit 32. As the paths in thestate 00 at the time t+1, two paths may be considered: the path of thecase where the branch metric BM00 is selected at the state 00 at thetime t and the path of the case where the branch metric BM11 is selectedat a state 01 at the time t. The value obtained by adding the value ofthe branch metric BM00 to the state metric of the state 00 at the time tand the value obtained by adding the value of the branch metric BM11 tothe state metric of the state 01 at the time t are compared and the pathwith the smaller value is used as the state metric of the state 00 atthe time t+1.

Similarly, the state metrics of the states 01, 10, and 11 at the timet+1 are calculated.

The ACS circuit 32, as described above, controls the path memory 33while inferring the state transition at the coding side (transmissionside). If there is no noise or distortion on the channel, the inputsignal matches with the original transmission signal point, so the BMgenerator 31 generates 0 for the branch metric relating to thetransmission signal point and the square of the distance between thesignal points for other branch metrics. Therefore, when these branchmetrics are cumulatively added in accordance with the state transitiondiagram and the state metric calculated in the ACS circuit 32, the statemetric remains 0 for the original path, but the state metric is a largevalue for other paths, so the transmission signal sequence can beinferred from this.

Here, consider the case where the input signal includes noise. Since theinput signal is comprised of the original transmission signal point plusnoise, the branch metric relating to the original transmission signalpoint does not always become 0 and has indefiniteness depending on thenoise power. In the same way, for other branch metrics as well, thesquare of the distance between signal points also has indefinitenessdepending on the noise power.

However, when the noise power is small, the ACS circuit 32 cumulativelyadds the branch metrics in accordance with the state transition diagramand calculates the state metric. Since the state metric is a small valuefor the original path, but the state metric has a large value for otherpasses, it is possible to estimate the transmission signal sequence.

FIG. 10 is a block diagram of the configuration of the ACS circuit 32.The ACS circuit 32 is comprised of the state 00 generating unit 41,state 01 generating unit 42, state 10 generating unit 43, and state 11generating unit 44 for finding the state metrics for the states 00, 01,10, and 11. The state 00 generating unit 41 is comprised of adders 45-1and 46-1 and a selector 47-1. The state metric of the state 00 andbranch metric BM00 at the time t are input to the adder 45-1 and added.In the same way, the state metric of the state 01 and branch metric BM11at the time t are input to the adder 46-1 and added.

The selector 47-1 compares the values input from the adder 45-1 and theadder 46-1 and outputs the smaller value to a register 48-1. Theregister 48-1 stores the value of the state metric of the state 00 atthe time t+1, output from the selector 47-1, as a value at the time whenfinding the state metric of the state 00 at the next time t+2, andoutputs it to the path memory 33.

The state 01 generating unit 42 is comprised of the adders 45-2 and 46-2and the selector 47-2. The state metric of the state 10 and branchmetric BM10 at the time t are input to the adder 45-2 and added. Thestate metric of the state 11 and the branch metric BM01 at the time tare input to the adder 46-2 and added. The selector 47-2 compares thevalues input from the adder 45-2 and the adder 46-2 and outputs thesmaller value to a register 48-2. The register 48-2 stores the value ofthe state metric of the state 01 at the time t+1, output from theselector 47-2, as a value at the time when finding the state metric ofthe state 01 at the next time t+2, and outputs it to the path memory 33.

The state 10 generating unit 43 is comprised of the adders 45-3 and 46-3and the selector 47-3. The state metric of the state 00 and the branchmetric BM11 at the time t are input to the adder 45-3 and added. Thestate metric of the state 01 and the branch metric BM00 at the time tare input to the adder 46-3 and added. The selector 47-3 compares thevalues input from the adder 45-1 and the adder 46-3 and outputs thesmaller value to a register 48-3. The register 48-3 stores the value ofthe state metric of the state 10 at the time t+1, output from theselector 47-3, as a value at the time when finding the state metric ofthe state 10 at the next time t+2, and outputs it to the path memory 33.

The state 11 generating unit 44 is comprised of the adders 45-3 and 46-3and the selector 47-4. The state metric of the state 10 and the branchmetric BM01 at the time t are input to the adder 45-4 and added, whilethe state metric of the state 11 and branch metric BM10 at the time tare input to the adder 46-4 and added. The selector 47-4 compares thevalues input from the adder 45-1 and the adder 46-4 and outputs thesmaller value to a register 48-4. The register 48-4 stores a value ofthe state metric of the state 11 at the time t+1, output from theselector 47-4, as the value at the time when finding the state metric ofthe state 11 at the next time t+2, and outputs it to the path memory 33.

However, the bit length in the above ACS circuit 32 is limited, sooverflow occurs due to the addition of the branch metrics, thereforeprocessing is necessary to prevent overflow from occurring. Theprocessing to prevent overflow from occurring in this way is called“normalization”. FIG. 11 shows the configuration of the ACS circuit 32for calculating a state metric while performing normalization.

In the configuration of the ACS circuit 32 shown in FIG. 11, the valueoutput from the state 00 generating unit 41 is supplied to the register48-1 through the subtracter 51-1, the value output from the state 01generating unit 42 is supplied to the register 48-2 through thesubtracter 51-2, the value output from the state 10 generating unit 43is supplied to the register 48-3 through the subtracter 51-3, and thevalue output from the state 11 generating unit 44 is supplied to theregister 48-4 through the subtracter 51-4. The values output from theregisters 48-1 to 48-4 are input to the path memory 33 and the minimumvalue processor 52.

The minimum value processor 52 calculates the minimum value of the statemetrics output from the registers 48-1 to 48-4 and outputs the value tothe subtracters 51-1 to 51-4, the path memory 33, and the monitoringcircuit 11. The subtracters 51-1 to 51-4 subtract the value input fromthe minimum value processor 52 from the values input from the stategenerating units 41 to 44 respectively corresponding to the subtracters51-1 to 51-4. In this way, normalization is carried out.

FIG. 12 is a block diagram of the configuration of the monitoringcircuit 11. The monitoring circuit 11 is comprised of an accumulator 61and a table 62. The accumulator 61 cumulatively adds the values of theminimum state metric for a predetermined time and outputs the cumulativetotal to the table 62. The table 62 is comprised of a ROM (read onlymemory) and the like and determines the noise of the channel by using atable establishing correspondence between a value output from theaccumulator 61 and noise.

FIG. 13 is a block diagram of the configuration of the accumulator 61. Atimer 71 generates a pulse at a predetermined cycle and supplies thepulse to a minimum SM (status metric) value accumulator 72. The minimumSM value accumulator 72 receives as input the minimum value of the statemetric output from the minimum value processor 52 (FIG. 11) and thevalue output and fed back from the minimum SM value accumulator 72. Thevalue output from the minimum SM value accumulator 72 and the pulsegenerated at the timer 71 are supplied to the register 73.

The operation of the accumulator 61 shown in FIG. 13 will be explainedreferring to the timing chart in FIGS. 14A to 14D. The pulse generatedby the timer 71 (FIG. 14A) is a reset pulse for resetting the cumulativetotal of the minimum SM values. The minimum SM value accumulator 72cumulatively adds the minimum SM values input between the pulsegenerated at a predetermined time t and the pulse generated at the nexttime t+1 and outputs the value to the register 73.

When the minimum SM value accumulator 72 receives as input a value suchas shown in FIG. 14B as the minimum SM value, a cumulative value shownin FIG. 14C is output. That is, when receiving as input a pulse from thetimer 71 at the time t, the minimum SM value accumulator 72 resets thecumulative total to 0. It then successively cumulatively adds theminimum SM values input between t and t+1. Further, when a pulse fromthe timer 71 is input again at the time t+1, the cumulative total isreset to 0.

The register 73 stores the value input from the minimum SM valueaccumulator 72 at the time when the pulse is input from the timer 71 andoutputs the value to the table 62.

FIGS. 15A and 15B are views of an example of a table stored in the table62. When the transmission system is QPSK and the coding rate R is 1/2,the magnitude of the transmission error rate (C/N) of data on thechannel is judged in accordance with the table shown in FIG. 15A. Whenthe transmission system is QPSK and the coding rate R is 3/4, themagnitude of the transmission error rate of the data on the channel isjudged in accordance with the table shown in FIG. 15B.

Judging the error rate on the channel as described above required theminimum value processor 52 for calculating the value of the minimumstate metric, the minimum SM value accumulator 72 provided at themonitoring circuit 11 and cumulatively adding the output from theminimum value processor 52, and the register 73 for storing thecumulative total. There was the problem that these circuits(apparatuses) 52, 72, and 73 became larger in circuit size along with anincrease in the number of transmission signal points (number of states)transmitted from the transmitter 1 (four states in the above example).

Further, there was the problem that the calculation time also increasedalong with an increase in the number of states. Furthermore, in the BStransmission system, it is being proposed to transmit using differenttransmission systems for time division. When a plurality of transmissionsystems are used, there was the problem that, with the monitoringcircuit 11 shown in FIG. 12, it became difficult to judge thetransmission error rate.

DISCLOSURE OF THE INVENTION

An object of the present invention is to provide an error rateestimating device used for a receiver which enables a shortening of thecalculation time and a reduction of the circuit scale by judging theerror rate on a channel using the number of times of normalizationperformed in a circuit for finding a state metric.

Another object of the present invention is to provide a receiver usingthe above error rate estimating device.

Still another object of the present invention is to provide an errorrate estimating method enabling a shortening of the calculation timewhen judging the error rate on the channel using the number of times ofnormalization performed in a circuit for finding a state metric.

Still another object of the present invention is to provide a decodingmethod using the above possible error rate estimating method.

Still another object of the present invention is to provide aninformation recording medium provided with software for executing amethod for realizing the above error rate estimating method and decodingmethod.

According to a first aspect of the present invention, there is providedan error rate estimating device for estimating the error rate of anquadrature-modulated signal when decoding the signal, the error rateestimating device provided with a counting means for counting the numberof times of normalization, performed when generating a state metric,within a predetermined time and an estimating means for estimating theerror rate of the signal from the correspondence between the number oftimes of normalization and the error rate respectively determined foreach different transmission system or each different coding rate basedon the number of times of normalization counted by the counting means.

Preferably, the estimating means estimates the error rate based on atable establishing correspondence between the number of times ofnormalization and the error rate on a channel.

Alternatively, preferably the estimating means inserts the number oftimes of normalization counted by the counting means into apredetermined function.

Alternatively, the counting means counts only the number of times ofnormalization for a signal of a predetermined transmission system or apredetermined coding rate.

According to a second aspect of the present invention, there is providedan error rate estimating method for estimating an error rate of a signalwhen decoding an quadrature-modulated signal, the error rate estimatingmethod comprising (1) a counting step of counting the number of times ofnormalization, performed when generating a state metric, within apredetermined time and (2) an estimating step (3) of estimating theerror rate of the signal from the correspondence between the number oftimes of normalization and the error rate respectively determined foreach different transmission system or each different coding rate basedon the number of times of normalization counted in the counting step.

Preferably, in the estimating step, the error rate is estimated based ona table establishing correspondence between the number of times ofnormalization and the error rate on a channel.

Alternatively, preferably, in the estimating step, the number of timesof normalization counted in the counting step is inserted into apredetermined function.

Alternatively, in the counting step, only the number of times ofnormalization for a signal of a predetermined transmission system or apredetermined coding rate is counted.

According to a third aspect of the present invention, there is providedan information recording medium for providing information for controlexecuted by a receiver receiving and decoding an quadrature-modulatedsignal transmitted through a channel, wherein the control informationincludes a count instruction for counting the number of times ofnormalization, performed when generating a state metric, within apredetermined time and an estimation instruction for estimating theerror rate of the signal from the correspondence between the number oftimes of normalization and the error rate respectively determined foreach different transmisssion system or each different coding rate basedon the number of times of normalization counted when the countinstruction is executed.

According to a fourth aspect of the present invention, there is providedan error rate estimating device for estimating an error rate of a signalwhen decoding a signal modulated by a plurality of transmission systemsor coding rates, the error rate estimating device provided with ajudging means for judging a transmission system or coding rate of thesignal; a counting means for counting the number of times ofnormalization, performed when generating a state metric, for each of theplurality of transmission systems or coding rates; an estimating meansfor estimating the error rate for each signal from the correspondencebetween the number of times of normalization and the error raterespectively determined for each different transmission system or eachdifferent coding rate based on the number of times of normalizationcounted by the counting means; and a selecting means for selecting oneof a plurality of error rates for each signal estimated by theestimating means.

Preferably, the selecting means selects the error rate according to thetransmission system or the coding rate judged by the judging means.

Alternatively, preferably the selecting means selects an error rate tobe output by comparing a plurality of error rates input with apredetermined reference value.

According to a fifth aspect of the present invention, there is providedan error rate estimating method for estimating an error rate of a signalwhen decoding a signal modulated by a plurality of transmission systemsor coding rates, the error rate estimating method comprising (1) ajudging step of judging a transmission system or coding rate of thesignal; (2) a counting step of counting the number of times ofnormalization, performed when a state metric is generated, for each ofthe plurality of transmission systems or coding rates; (3) an estimatingstep of estimating the error rate for each signal each signal from thecorrespondence between the number of times of normalization and theerror rate respectively determined for each different transmissionsystem or each different coding rate based on the number of times ofnormalization counted in the counting step; and (4) a selecting step ofselecting one of a plurality of error rates for each signal estimated inthe estimating step.

Preferably, in the selecting step, the error rate is selected accordingto the transmission system or the coding rate judged by the judgingstep.

Alternatively, preferably, in the selecting step, an error rate to beoutput is selected by comparing a plurality of error rates input with apredetermined reference value.

According to a sixth aspect of the present invention, there is providedan information recording medium for providing information for controlexecuted by a receiver receiving a signal modulated by a plurality oftransmission systems or coding rates sent through a channel, wherein thecontrol information includes a judgement instruction for judging atransmission system or coding rate of the signal; a count instructionfor counting the number of times of normalization, performed whengenerating a state metric, within a predetermined time; an estimationinstruction for estimating the error rate of the signal from thecorrespondence between the number of times of normalization and theerror rate respectively determined for each different transmissionshystem or each different coding rate based on the number of times ofnormalization counted in the count step; and a selection instruction forselecting one of a plurality of error rates for each signal estimated inthe estimating step.

According to a seventh aspect of the present invention, there isprovided an error rate estimating device for estimating an error rate ofa signal when decoding a signal modulated by a plurality of transmissionsystems or coding rates, the error rate estimating device comprising acounting means for counting the number of times of normalization,performed when generating a state metric, for each of the plurality oftransmission systems or coding rates; an estimating means for estimatingthe error rate for each signal by the number of times of normalizationcounted by the counting means; a multiplying means for determining avalue for multiplication with the error rate for each signal accordingto a value of the error rate estimated by the estimating means for apredetermined transmission system or coding rate among the transmissionsystems or coding rates and multiplying with that value; and anoutputting means for adding and outputting the error rate for eachsignal output from the multiplying means.

According to an eighth aspect of the present invention, there isprovided an error rate estimating method for estimating an error rate ofa signal when decoding a signal modulated by a plurality of transmissionsystems or coding rates, the error rate estimating method comprising (1)a counting step of counting the number of times of normalization,performed when generating a state metric, for each of the plurality oftransmission systems or coding rates; (2) an estimating step ofestimating the error rate for each signal by the number of times ofnormalization counted in the counting step; (3) a multiplying step ofdetermining a value for multiplication with the error rate for eachsignal according to a value of the error rate estimated by theestimating step for a predetermined transmission system or coding rateamong the transmission systems or coding rates and multiplying with thatvalue; and (4) an outputting step of adding and outputting the errorrate for each signal output in the multiplying step.

According to a ninth aspect of the present invention, there is providedan information recording medium for providing information for controlexecuted by a receiver receiving and decoding a signal modulated by aplurality of transmission systems or coding rates sent through achannel, the control information including a count instruction forcounting the number of times of normalization, performed when generatinga state metric, for each of the plurality of transmission systems orcoding rates; an estimation instruction for estimating the error ratefor each signal by the number of times of normalization counted in thecounting step; a multiplication instruction for determining a value formultiplication with the error rate for each signal according to a valueof the error rate estimated by the estimating step for a predeterminedtransmission system or coding rate among the transmission systems orcoding rates and multiplying with that value; and an output instructionfor adding and outputting the error rate for each signal output from themultiplying step.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the configuration of a transmitter and areceiver.

FIG. 2 is a block diagram of the configuration of the encoder of FIG. 1.

FIGS. 3A and 3B are views for explaining a puncturing unit of FIG. 1.

FIGS. 4A and 4B are views for explaining the input/output data of thepuncturing unit.

FIG. 5 is a view for explaining the arrangement of signal points by themapping unit of FIG. 1.

FIGS. 6A and 6B are views for explaining a bit insertion unit of FIG. 1.

FIGS. 7A and 7B are views for explaining the input/output data of thebit insertion unit.

FIG. 8 is a block diagram of the configuration of the decoder of FIG. 1.

FIG. 9 is a trellis diagram.

FIG. 10 is a block diagram of the configuration of the ACS circuit ofFIG. 8.

FIG. 11 is a block diagram of the configuration of an ACS circuitperforming normalization.

FIG. 12 is a block diagram of the configuration of the monitoringcircuit of FIG. 8.

FIG. 13 is a block diagram of the configuration of the accumulator ofFIG. 12.

FIGS. 14A to 14D are timing charts for explaining an operation of theaccumulator of FIG. 13.

FIGS. 15A and 15B are views of a table stored in the table of FIG. 12.

FIG. 16 is a block diagram of the configuration of the ACS circuit ofthe present invention.

FIG. 17 is a block diagram of the configuration of the monitoringcircuit to which the present invention is applied.

FIG. 18 is a block diagram of the configuration of a normalizationaccumulator in FIG. 17.

FIGS. 19A to 19D are timing charts for explaining the operation of thenormalization accumulator in FIG. 18.

FIGS. 20A and 20B are views of a table stored in the table of FIG. 17.

FIGS. 21A and 21B are views of a table stored in the table of FIG. 17.

FIG. 22 is a block diagram of another configuration of the monitoringcircuit.

FIG. 23 is a graph illustrating the function of the function processorof FIG. 22.

FIG. 24 is a view for explaining a frame structure of a different codingrate.

FIG. 25 is a view for explaining another configuration of the decoder.

FIG. 26 is a block diagram of the configuration of the monitoringcircuit of FIG. 25.

FIG. 27 is a block diagram of the configuration of the normalizationaccumulator of FIG. 26.

FIGS. 28A to 28F are timing charts for explaining an operation of thenormalization accumulator of FIG. 27.

FIG. 29 is a block diagram of another example of the configuration ofthe monitoring circuit.

FIG. 30 is a block diagram of still another example of the configurationof the monitoring circuit.

FIG. 31 is a view of the configuration of the selector of FIG. 30.

FIG. 32 is a view of the configuration of the selector of FIG. 30.

FIG. 33 is a view of a table stored in the selector of FIG. 30.

FIG. 34 is a view of a table stored in the selector of FIG. 30.

FIG. 35 is a block diagram of the configuration of the monitoringcircuit and the receiver when simultaneously receiving signals ofdifferent coding rates.

FIG. 36 is a block diagram of the configuration of the monitoringcircuit of FIG. 35.

FIG. 37 is a view of a table stored in the selector of FIG. 36.

FIG. 38 is a view explaining the hardware configuration when realizingthe coding processing by software.

FIG. 39 is a view explaining the hardware configuration when realizingthe decoding processing by software.

BEST MODE FOR CARRYING OUT THE INVENTION

A transmitter and receiver to which the present invention is applied arebasically configured the same as in the configuration shown in FIG. 1,therefore explanations thereof are omitted. The method of judging theerror rate on the channel performed at the receiver side in the presentinvention differs from that explained above. First, the configuration ofthe ACS circuit 32 of the decoder 9 will be explained with reference toFIG. 16.

FIG. 16 is a block diagram of the configuration of the ACS circuit 32for performing normalization using the data of the upper bits of thestate metrics of all states to find a state metric. The most significantbit of the N number of bits of data output from the state 00 generatingunit 41 for generating the state metric of the state 00 is input to theregister 48-1 through an EXOR (exclusive OR) circuit 81-1 forcalculating the exclusive OR. The N−1 number of bits other than the mostsignificant bit are input to the register 48-1 without going through theEXOR circuit 81-1. Data from the AND circuit 82 for calculating the ANDis input to the EXOR circuit 81-1 as well. Data output from the register48-1 is supplied to the path memory 33, while the most significant bitis supplied to the AND circuit 82.

In the same way, the most significant bit among the N number of bits ofdata output from the state 01 generating unit 42 is input to theregister 48-2 through the EXOR circuit 81-2, while the N−1 number ofbits other than the most significant bit are input to the register 48-2without going through the EXOR circuit 81-2. Data from the AND circuit82 is input to the EXOR circuit 81-2. Data output from the register 48-2is supplied to the path memory 33, while the most significant bit issupplied to the AND circuit 82.

In addition, the most significant bit of the N number of bits of dataoutput from the state 10 generating unit 43 is input to the register48-3 through the EXOR circuit 81-3, while the N−1 number of bits otherthan the most significant bit are input to the register 48-3 withoutgoing through the EXOR circuit 81-3. Data from the AND circuit 82 isinput to the EXOR circuit 81-3 as well. Data output from the register48-3 is supplied to the path memory 33, while the most significant bitis supplied to the AND circuit 82.

Further, the most significant bit of the N number of bits of data outputfrom the state 11 generating unit 44 is input to the register 48-4through the EXOR circuit, while the N−1 number of bits other than themost significant bit is input to the register 48-4 without going throughthe EXOR circuit. Data output from the AND circuit 82 is input to theEXOR circuit 81-4 as well. Data output from the register 48-4 issupplied to the path memory 33, and the most significant bit is suppliedto the AND circuit 82.

The AND circuit 82 outputs 1 when all of the most significant bits ofdata output from the registers 48-1 to 48-4 are 1 and outputs 0 at othertimes. When the values of the state metrics of the states graduallyincrease and the most significant bit of the minimum state metricbecomes 1, it uses an exclusive OR operation (EXOR circuits 81-1 to81-4) to make the most significant bits of the state metrics of allstates 0 for normalization.

FIG. 17 is a block diagram of the configuration of the monitoringcircuit 11. The monitoring circuit 11 is comprised of a normalizationaccumulator 91 and a table 92. The normalization information is inputfrom the ACS circuit 32 to the normalization accumulator 91. Thenormalization information is information output to the monitoringcircuit 11 each time the normalization is performed by the ACS circuit32.

FIG. 18 is a block diagram of the configuration of the normalizationaccumulator 91. The normalization accumulator 91 is comprised of a timer101, a normalization cumulative counter 102, and a register 103.Normalization information output from the ACS circuit 32 is input to thenormalization cumulative counter 102. A pulse generated by the timer 101every predetermined time is input to the normalization cumulativecounter 102 as well. The pulse generated by the timer 101 is output tothe register 103 as well. The output from the normalization cumulativecounter 102 is input to the register 103 as well.

The operation of the normalization accumulator 91 shown in FIG. 18 willbe explained referring to the timing chart in FIGS. 19A to 19D. As shownin FIG. 19A, a pulse is generated for every time unit by the timer 101,and the generated pulse is supplied to the normalization cumulativecounter 102 and the register 103. As shown in FIG. 19B, thenormalization cumulative counter 102 counts the number of times of inputwhen the normalization information is output from the ACS circuit 32. Inthe example shown in FIGS. 19A to 19D, eight times of normalizationinformation are input during one time unit.

The normalization cumulative counter 102 outputs the counter value tothe register 103 and resets its value to 0 (FIG. 19D) for every pulsesupplied from the timer 101. In this way, the counter value output toand stored in the register 103 is output to the table 92 when the pulsefrom the timer 101 is input.

FIGS. 20A and 20B are views of examples of tables stored by the table92. The table shown in FIGS. 20A and 20B shows the correspondencebetween the counter value (count) output from the register 103 of thenormalization accumulator 91 and the value of the transmission errorrate (BER: bit error rate) of the channel 6 estimated from the count.FIG. 20A is a table in the case where the transmission system is theQPSK system and the coding rate R is 1/2, while FIG. 20B is a table inthe case where the transmission system is the QPSK system and the codingrate R is 3/4.

For instance, in the case where the transmission system is the QPSKsystem and the coding rate R is 1/2, when the count supplied from theregister 103 is 355 or more, the value output as the error rateinformation 12 of the channel 6 (FIG. 1) is 0.50×10⁻³. In the same way,a value calculated based on the table from the transmission system,coding rate, and a value corresponding to the count is output as theerror rate information 12.

FIGS. 21A and 21B show tables in the case where the CN ratio (carrier tonoise ratio) is output as the error rate information 12. FIG. 21A is atable when the transmission system is the QPSK system and the codingrate R is 1/2, while FIG. 21B is a table when the transmission system isthe QPSK system and the coding rate R is 3/4. For instance, in the casewhere the transmission system is the QPSK system and the coding rate Ris 1/2, when the count supplied from the register 103 is 355 or more,the value output as the error rate information 12 of the channel 6 is3.00 (dB).

FIG. 22 is a block diagram of another configuration of the monitoringcircuit 11. The monitoring circuit 11 shown in FIG. 22 is comprised of,the normalization accumulator 91 and a function processor 111. Thefunction processor 111 estimates the error rate information 12 withoutusing the tables shown in FIGS. 20A and 20B and FIGS. 21A and 21B, butby using the function f calculated from these tables.

In the table shown in FIG. 20A in the case where the transmission systemis the QPSK system and the coding rate R is 1/2, BER is 1.09×10⁻³ whenthe count is from 345 to 354 (representative value of 350) and BER is0.80×10⁻² when the count is from 335 to 344 (representative value of340). In the other words, it is learned that if the count is reduced by10 from 350 to 340, the value of BER increases by about four times.Calculating the equation used in the function processor 111 consideringthis fact gives the following equation (1):f(input)=0.0005×4^(((360−input)/10))  (1)In equation (1), the above “input” shows the count input from thenormalization accumulator 91.

Note that in equation (1), the range of the count able to be used asinput is from 335 to 354. When the count is 334 or less, 0.2×10⁻¹ isoutput as the error rate information 12, while when the count is 355 ormore, 0.5×10⁻³ is output as the error rate information 12.

This is because a difference arises between the value obtained from thefunction f and the value used when preparing a table (function f nolonger followed). In this way, in the practical range, the function f isused in the range where there is no problem, while a value based on thecount is output in other ranges.

In the same way, the following equation (2) is derived as a function fcorresponding to the table of FIG. 20B in the case where thetransmission system is the QPSK system and the coding rate is 3/4:f(input)=0.0033×3^(((580−input)/10))  (2)In equation (2), the range of the count able to be used as the input is545 to 565. When the count is 544 or less, 1.90×10⁻¹ is output as theerror rate information 12, while when the count 565 or more, 4.80×10⁻³is output as the error rate information 12.

The following equation (3) is derived as a function f corresponding tothe table shown in FIG. 21A in the case where the transmission system isthe QPSK system and the coding rate is 1/2.f(input)=0.05^((input−300))  (3)In equation (3), the range of the count able to be used as the input is335 to 355. When the count is 334 or less, 1.50 is output as the errorrate information 12, while when the count is 355 or more, 3.00 is outputas the error rate information 12.

The following equation (4) is derived as a function f corresponding tothe table shown in FIG. 21B in the case where the transmission system isthe QPSK system and the coding rate is 3/4.f(input)=0.025^((input−500))  (4)In equation (4), the range of the count able to be used as the input is544 to 565. When the count is 544 or less, 0.85 is output as the errorrate information 12, while when the count is 565 or more, 2.20 is outputas the error rate information 12.

FIG. 23 shows the relation between data serving as the basis whenpreparing a table and a graph obtained by any one equation amongequations (1) to (4). As will be understood from FIG. 23, equations (1)to (4) approximate the values of the table within the dotted lines.Outside of the dotted lines, since the equations do not approximate tothe values of the table, as described above, the error rate information12 is not obtained using equations (1) to (4), but a predetermined valueis output. Note that in practice, if the BER or C/N value obtained byequations (1) to (4) is sufficient, it is possible not to output theerror rate information 12 outside the range obtained by equations (1) to(4).

In the above explanation, the case where the transmission system was theQPSK system and the coding rate R was either of 1/2 or 3/4 wasexplained, but different transmission systems or coding rates R aremixed in some cases. For example, as shown in FIG. 24, the followingexplanation will be given taking as an example the case where thetransmission system is the QPSK system, but the coding rate R is amixture of 1/2 and 3/4.

FIG. 25 is a block diagram of the configuration of the decoder 9 and themonitoring circuit 11 in the case where different coding rates R aremixed together. In this configuration, the monitoring circuit 11receives as input information relating to the coding rate R from the bitinsertion unit 8 (FIG. 1). The bit insertion unit 8 judges the codingrate R, outputs a signal as is to the decoder 9 when a signal of acoding rate R of 1/2 is input, and inserts bits by depuncturing and thenoutputs the signal to the decoder 9 when a signal of a coding rate R of3/4 is input. The monitoring circuit 11 receives as input information ofthe judged coding rate R.

FIG. 26 is a block diagram of the configuration of the monitoringcircuit 11 shown in FIG. 25. The normalization accumulator 91 in thisconfiguration receives as input the normalization information from theACS circuit 32 and the coding rate information from the bit insertionunit 8.

FIG. 27 is a block diagram of the configuration of the normalizationaccumulator 91 shown in FIG. 26. In this configuration, the timer 101and the normalization cumulative counter 102 receive as input the codingrate information. The normalization cumulative counter 102 also receivesas input the normalization information and the pulses output from thetimer 101. The register 103 receives as input the output from thenormalization cumulative counter 102 and the pulses from the timer 101.

The operation of the normalization accumulator 91 shown in FIGS. 28A to28F will be explained next referring to the timing chart of FIG. 27. Theexplanation will be made of the case where the transmission system isthe QPSK system, but the coding rate R is changed in the order of 1/2,3/4, and 1/2 as shown FIG. 28A and the case where a pulse is generatedat the timer 101 as shown in FIG. 28B. The interval between the pulsegenerated at the timer 101 at a predetermined time and the pulse thenext time is defined as one time unit.

Here, for instance, if the coding rate information is made 1 when thecoding rate R is 1/2 and is made 0 when the coding rate R is 3/4, whenthe coding rate R changes as shown in FIG. 28A, the coding rateinformation becomes as shown in FIG. 28C. Further, as shown in FIG. 28D,when the normalization information is input a total of eight times in atime unit, that is, six times when the coding rate R is 1/2 and twotimes when the coding rate R is 3/4, in the normalization cumulativecounter 102, the normalization cumulative counter 102 counts only thenumber of times of normalization at the same coding rate R, in the otherwords, only the number of times of normalization when the coding rateinformation is 1.

That is, in the example shown in FIG. 28E, only the number of times ofnormalization when the coding rate R is 1/2 is counted, so the valueoutput to the table 92 from the register 103 as the number of times ofnormalization number for one time unit becomes six.

The table 92 uses the value input in this way and the stored table tocalculate and output the error rate information 12. As the tables whichthe table 92 stores, the table shown in FIGS. 20A and 20B or the tableshown in FIGS. 21A and 21B may be used. Further, it is possible to findthe error rate information 12 from the function f.

FIG. 29 is a block diagram of another configuration of the monitoringcircuit 11 for estimating the error rate information 12 when differenttransmission systems or coding rates R are mixed together. In thisconfiguration, the error rate information 12 is estimated separately forthe signals with the coding rate R of 1/2 and the signals with thecoding rate R of 3/4. A normalization accumulator 91-1 and anormalization accumulator 91-2 receive as input normalizationinformation from the ACS circuit 32. The coding rate information fromthe bit insertion unit 8 is supplied to the normalization accumulator91-2 and the selector 122 and is also supplied to the normalizationaccumulator 91-1 through a NOT circuit 121. The coding rate informationinput to the normalization accumulator 91-1 is input through the NOTcircuit 121, so information opposite to that of the normalizationaccumulator 91-2 is input.

The information output from the normalization accumulator 91-1 is inputto the table 92-1, while the information output from the normalizationaccumulator 91-2 is input to the table 92-2. The information output fromthe table 92-1 and table 92-2 is input to the selector 122. The selector122 selects and outputs one of the information input from the tables92-1 and 92-2 based on the input coding information.

The normalization accumulator 91-1 and the normalization accumulator91-2 are configured as shown in FIG. 12. The normalization accumulator91-1 counts the number of times of normalization input when the codingrate information is of the coding rate R of 1/2, while the normalizationaccumulator 91-2 counts the number of times of normalization input whenthe coding rate information is of the coding rate R of 3/4. As explainedabove, since the mutually opposite coding rate information input to thenormalization accumulator 91-1 and the normalization accumulator 91-2are input, when one of the number of times of normalization is beingcounted, the other is not counted.

The numbers of times of normalization counted by the normalizationaccumulators 91-1 and 91-2 in this way are output to the correspondingtables 92-1 and 92-2. The table 92-1 stores the tables shown in FIG. 20Aand FIG. 21A, while the table 92-2 stores the tables shown in FIG. 20Band FIG. 21B. The tables 92-1 and 92-2 estimate the error rateinformation 12 according to the tables they store and output the resultsto the selector 122. The selector 122 selects the input from the tables92-1 and 92-2 corresponding to the coding rate which the input codingrate information indicates and outputs the same as the error rateinformation 12.

FIG. 30 is a block diagram of another configuration of the monitoringcircuit 11. The selector 131 of this configuration selects and outputsan input from the tables 92-1 and 92-2 without using the codinginformation. The configuration of the selector 131 is shown in FIG. 31.The selector 131 stores the constant C. This constant C and the inputvalue are compared to determine the output information. That is, whenthe input 0 is made the input from the table 92-1 and the input 1 ismade the input from the table 92-2, the input O is output as the errorrate information 12 if input O is larger than the constant C, while theinput 1 is output as the error rate information 12 if the input O isequal to or less than the constant C.

FIG. 32 is a block diagram of another configuration of the selector 131.The selector 131 outputs a value giving a predetermined weight to theinput value. the multiplier 141-1 receives as input information from thetable 92-1, while the multiplier 141-2 receives as input the informationfrom the table 92-2. The multipliers 141-1 and 141-2 multiply the valuesinput to them with a predetermined value and output the results to anadder 142. The adder 142 adds and outputs the sum of the input values.

FIG. 33 is a table showing weighting values to be multiplied by themultipliers 141-1 and 141-2. The table is stored in a not shown storageunit and is supplied to the multipliers 141-1 and 141-2 of the selector131 in accordance with need. The table is a table corresponding to thetable shown in FIGS. 21A and 21B. The value for the weighting isdetermined based on the error rate information 12 of the coding rateR=1/2 (information output from the table 91-1). For instance, wheninformation from the table 92-1 input to the multiplier 141-1 is 2.5,1.0 is supplied as the weighting value to the multiplier 141-1 and 0.0is supplied as the weighting value to the multiplier 141-2.

FIG. 34 is another table of the weighting values. The table is a tablefor the case of weighting based on the information of the cumulativenumber of times of normalization when the coding rate R=3/4. Whenweighting in accordance with the table, the multipliers 141-1 and 141-2(FIG. 32) are supplied with output from the normalization accumulator91-2. The multipliers 141-1 and 141-2 weight the values input from thetables 92-1 and 92-2 based on the input normalization information andoutput the results. For example, when the information of the cumulativenumber of times of normalization output from the normalizationaccumulator 91-2 is 570, the multiplier 141-1 multiplies 0.0 with thevalue input from the table 92-1 by 0.0, the multiplier 141-2 multiplies1.0 with the value input from the table 92-2, and these output theresults to the adder 142.

In the above explanation, the tables 92-1 and 92-2 estimated the errorrate information 12 from the stored tables, but it is also possible toestimate this using the above functions. Namely, it is also possible touse a function processor using the function of equation (3) instead ofthe table 92-1 and use a function processor using a function of equation(2) instead of the table 92-2.

Next, a monitoring circuit 11 in the case of simultaneously receivingand processing two or more signals transmitted by different transmissionsystems (coding rates) will be explained. FIG. 35 is a block diagram ofthe configuration of a receiver including a monitoring circuit 11 whichsimultaneously receives and processes two or more signals transmitted bydifferent transmission systems. The monitoring circuit 11 receives asinput normalization information from the decoders 9 and 9′.

FIG. 36 is a block diagram of the configuration of the monitoringcircuit 11 of FIG. 35. The normalization accumulator 91-1 receives asinput the normalization information of the encoder 9, while thenormalization accumulator 91-2 receives as input the normalizationinformation of the coder 9′. The information output from thenormalization accumulator 91-1 is input to the table 92-1, while theinformation output from the normalization accumulator 91-2 is input tothe table 92-2. The information output from the tables 92-1 and 92-2 areinput to the selector 131.

The normalization accumulators 91-1 and 91-2 are configured is shown inFIG. 3. The normalization accumulator 91-1 cumulatively adds the numberof times of normalization for a signal of a coding rate R of 1/2, whilethe normalization accumulator 91-2 cumulatively adds the number of timesof normalization of a signal of a coding rate R of 3/4. The table 92-1stores the table of FIG. 21A, while the table 92-2 stores the table ofFIG. 21B. The selector 131 is configured as shown in FIG. 32, stores thetable shown in FIG. 37, weights the input value based on the storedtable, and outputs the result.

The table shown in FIG. 37 shows a table in the case of weighting basedon an estimated value of the error rate information 12 for a coding rateR=3/4 (information output from the table 92-2). For instance, when theestimated value output from the table 92-2 is 2.5, the selector 131multiplies 1.0 with the estimated value input from the table 92-1 basedon the table shown in FIG. 37, multiplies 0.0 with the estimated valueinput from the table 92-2, adds the values, and outputs the result.

As described above, since the error rate on the channel is calculatedbased on the number of times of normalization performed in the ACScircuit 32 for finding the state metric, the circuit can be made smallerand simpler. It is also possible to properly estimate the error rateinformation for a signal transmitted by different transmission systemsor coding rates.

Next, an explanation will be given, using FIG. 38, of the hardwareconfiguration of the transmitter 1 in the case of coding processingexplained using FIG. 1 to FIG. 37 by software.

In FIG. 38, the transmitter 1 is provided with a CPU (central processingunit) 1001 for executing a processing program, a ROM (read only memory)1002 storing a processing program for processing in accordance with acoding routine explained using FIG. 1 to FIG. 37, a RAM (random accessmemory) 1003 temporarily storing processing data, an external storage1004 storing data to be coded and transmitted, and a communications I/F(interface) 1005 for transmitting an I-signal and Q-signal of a signalpoint through the channel 6 to the receiver 7. Further, it is providedwith a path 1006 connected to the circuits for transmission of theprogram or data.

The external storage 1004 is a randomly accessible information storagemedium such as a magnetic disk or optical disk.

Note that the processing program of the present embodiment is stored inthe ROM 1002 in this configuration, but it is also possible to have itstored in an external storage 1004 and to transfer it through the bus1006 to the RAM 1003 at the time of execution and execute it by the CPU1001. Further, it is also possible to configure the communications I/F1005 to be able to transmit and receive a signal, have the processingprogram received by the communications I/F 1005 from the externalstorage through the channel, store it in the RAM 1003 or the externalstorage 1004, and execute it at the CPU 1001.

That is, the transmitter 1 may introduce the computer program for theabove processing for processing at the CPU 1001 through not only amedium comprised of a magnetic disk, CD-ROM, or other informationstorage medium, but also the Internet, digital satellite, or othertransmission medium.

An explanation will be given, using FIG. 39, of the hardwareconfiguration of the receiver 1 in the case of decoding processingexplained using FIG. 1 to FIG. 37 by software.

In FIG. 39, the receiver 7 is provided with a CPU (central processingunit) 2001 for executing a processing program, a ROM (read only memory)2002 storing a processing program for processing in accordance with adecoding routine explained using FIG. 1 to FIG. 37, a RAM (random accessmemory) 2003 temporarily storing processing data, an external storage2004 storing data to be decoded, that is, decoding information 10, and acommunications I/F (interface) 2005 for receiving an I-signal andQ-signal from the transmitter 1 through the channel 6. Further, it isprovided with a path 2006 connected to the circuits for transmission ofthe program or data.

The external storage 2004 is a randomly accessible information storagemedium such as a magnetic disk or optical disk.

Note that the processing program of the present embodiment is stored inthe ROM 2002 in this configuration, but it is also possible to have itstored in an external storage 2004 and to transfer it through the bus2006 to the RAM 2003 at the time of execution and execute it by the CPU2001. Further, it is also possible to configure the communications I/F2005 to be able to transmit and receive a signal, have the processingprogram received by the communications I/F 2005 from the externalstorage through the channel, store it in the RAM 2003 or the externalstorage 2004, and execute it at the CPU 2001.

That is, the receiver 7 may introduce the computer program for the aboveprocessing for processing at the CPU 2001 through not only a mediumcomprised of a magnetic disk, CD-ROM, or other information storagemedium, but also the Internet, digital satellite, or other transmissionmedium.

As explained above, according to the above embodiment using the errorrate estimating device, the error rate estimating method, and the mediumof the present invention, since the number of times of normalizationperformed when generating a state metric is counted within apredetermined time and the error rate of a signal is estimated by thecounted number of times of normalization, the device for estimating theerror rate of the signal can be made smaller in configuration and canperform processing at a high speed.

Further, according to the above embodiment using the error rateestimating device, the error rate estimating method, and the medium ofthe present invention, since the number of times of normalizationperformed when generating a state metric is counted for each of aplurality of transmission systems or coding rates and the error rate foreach signal is estimated by the counted number of times ofnormalization, the device for estimating the error rate of the signalcan be made smaller in configuration and can perform processing at ahigh speed.

Further, according to the above embodiment utilizing the error rateestimating device, error rate estimating method, and medium of thepresent invention, since the number of times of normalization performedwhen generating a state metric is counted for each of a plurality oftransmission systems or coding rates, the error rate for each signal isestimated by the counted number of times of normalization, a value to bemultiplied with an error rate for each signal is determined inaccordance with the value of the error rate estimated by the estimatingmeans for a predetermined transmission system or coding rate andmultiplied, and the value is added and output, the device for estimatingthe error rate of the signal can be made smaller in configuration andcan perform processing at a high speed.

INDUSTRIAL APPLICABILITY

The error rate estimating device and the error rate estimating method ofthe present invention may be applied to various apparatuses fortransmitting signals.

1. An error rate estimating device for estimating an error rate of asignal when decoding a signal modulated by a plurality of transmissionsystems or coding rates, said error rate estimating device providedwith: a judging means for judging a transmission system or coding rateof the signal; a counting means for counting a number of timesnormalization is performed in a predetermined time period for each ofthe plurality of transmission systems or coding rates; state metriccalculating means for calculating a state metric, wherein normalizationis being performed while said state metric is being calculated; anestimating means for estimating the error rate for each signal from thecorrespondence between the number of times of normalization and theerror rate respectively determined for each different transmissionsystem or each different coding rate based on the number of times ofnormalization counted by the counting means; and a selecting means forselecting one of a plurality of error rates for each signal estimated bythe estimating means.
 2. An error rate estimating device as set forth inclaim 1, wherein said selecting means selects the error rate accordingto the transmission system or the coding rate judged by the judgingmeans.
 3. An error rate estimating device as set forth in claim 1,wherein the selecting means selects an error rate to be output bycomparing a plurality of error rates input with a predeterminedreference value.
 4. An error rate estimating method for estimating anerror rate of a signal when decoding a signal modulated by a pluralityof transmission systems or coding rates, said error rate estimatingmethod comprising: a judging step of judging a transmission system orcoding rate of the signal; a counting step of counting a number of timesnormalization is performed in a predetermined time period, for each ofthe plurality of transmission systems or coding rates; a state metriccalculating step for calculating a state metric for each of theplurality of transmission systems or coding rates, wherein normalizationis being performed while said state metric is being calculated; anestimating step of estimating the error rate for each signal from eachof the plurality of transmission systems or coding rates using thenumber of times normalization is performed; and a selecting step ofselecting one of a plurality of error rates for each signal estimated inthe estimating step.
 5. An error rate estimating method as set forth inclaim 4, further comprising, in said selecting step, selecting the errorrate according to the transmission system or the coding rate judged bythe judging step.
 6. An error rate estimating method as set forth inclaim 4, further comprising, in said selecting step, selecting an errorrate to be output by comparing a plurality of error rates input with apredetermined reference value.
 7. An information recording medium forproviding information for control executed by a receiver receiving asignal modulated by a plurality of transmission systems or coding ratessent through a channel, wherein said control information includes: ajudgment instruction for judging a transmission system or coding rate ofthe signal; a count instruction for counting a number of timesnormalization is performed in a predetermined time period; a calculationinstruction for calculating a state metric; wherein normalization isbeing performed while said state metric is being calculated; anestimation instruction for estimating the error rate of the signal usingthe number of times normalization is performed; and a selectioninstruction for selecting one of a plurality of error rates for eachsignal estimated in the estimating step.
 8. An error rate estimatingdevice for estimating an error rate of a signal when decoding a signalmodulated by a plurality of transmission systems or coding rates, saiderror rate estimating device comprising: a counting means for counting anumber of times normalization is performed in a predetermined timeperiod, for each of the plurality of transmission systems or codingrates; state metric calculating means for calculating a state metric,wherein normalization is being performed while said state metric isbeing calculated; an estimating means for estimating the error rate foreach signal from each of the plurality of transmission systems or codingrates using the number of times normalization is performed; amultiplying means for determining a value for multiplication with theerror rate for each signal according to a value of the error rateestimated by the estimating means for a predetermined transmissionsystem or coding rate among the transmission systems or coding rates andmultiplying with that value; and an outputting means for adding andoutputting the error rate for each signal output from the multiplyingmeans.
 9. An error rate estimating method for estimating an error rateof a signal when decoding a signal modulated by a plurality oftransmission systems or coding rates, said error rate estimating methodcomprising: a counting step of counting the number of timesnormalization is performed in a predetermined time period, for each ofthe plurality of transmission systems or coding rates; a state metriccalculating step for calculating a state metric for each of theplurality of transmission systems or coding rates, wherein normalizationis being performed while said state metric is being calculated; anestimating step of estimating the error rate for each signal from eachof the plurality of transmission systems or coding rates using thenumber of times normalization is performed; a multiplying step ofdetermining a value for multiplication with the error rate for eachsignal according to a value of the error rate estimated by theestimating step for a predetermined transmission system or coding rateamong the transmission systems or coding rates and multiplying with thatvalue; and an outputting step of adding and outputting the error ratefor each signal output in the multiplying step.
 10. An informationrecording medium for providing information for control executed by areceiver receiving and decoding a signal modulated by a plurality oftransmission systems or coding rates sent through a channel, saidcontrol information including: a count instruction for counting a numberof times normalization is performed, for each of the plurality oftransmission systems or coding rates; a calculation instruction forcalculating a state metric, wherein normalization is being performedwhile said state metric is being calculated; an estimation instructionfor estimating the error rate for each signal using the number of timesnormalization is performed; a multiplication instruction for determininga value for multiplication with the error rate for each signal accordingto a value of the error rate estimated by the estimating step for apredetermined transmission system or coding rate among the transmissionsystems or coding rates and multiplying with that value; and an outputinstruction for adding and outputting the error rate for rach signaloutput from the multiplying step.